Physical Implementation
Physical implementation is the process of translating a high-level circuit design into a manufacturable layout, ensuring the design meets performance, power, and area (PPA) goals. This stage involves placing and routing components, optimizing timing, power distribution, and signal integrity, while adhering to manufacturing constraints such as design rules and process technology requirements.
Floorplanning
Develops an optimized floorplan to ensure efficient power delivery, minimal routing complexity, and balanced performance across the chip.
Placement
Standard cells and macros are strategically placed to optimize timing, minimize congestion, and ensure efficient routing.
Routing
Efficient signal interconnections are created, minimizing congestion and optimizing for signal integrity.
Power Planning & Power Grid Design
Designs an efficient power distribution network to guarantee uniform power delivery and meet required power and thermal constraints.
Clock Tree Synthesis (CTS)
Builds a clock tree that balances skew, latency, and power to ensure timing synchronization throughout the chip.
Design Rule Checking (DRC) & Layout Versus Schematic (LVS)
Ensures layout accuracy by performing thorough DRC and LVS checks, adhering to foundry requirements.